PRCM Registers
www.ti.com
542
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Power, Reset, and Clock Management
15.6.12 DMACLKEN Register (offset = 48h) [reset = 0h]
DMACLKEN is shown in Figure 15-15 and described in Table 15-15.
Figure 15-15. DMACLKEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED DSLPCLKEN
R-0h R/W-0h
15 14 13 12 11 10 9 8
NU1 SLPCLKEN
R-0h R/W-0h
7 6 5 4 3 2 1 0
NU2 RUNCLKEN
R-0h R/W-0h
Table 15-15. DMACLKEN Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 DSLPCLKEN R/W 0h
UDMA_A_DSLP_CLK_ENABLE
0h = Disable UDMA_A clock during deep-sleep mode
1h = Enable UDMA_A clock during deep-sleep mode
15-9 NU1 R 0h
8 SLPCLKEN R/W 0h
UDMA_A_SLP_CLK_ENABLE
0h = Disable UDMA_A clock during sleep mode
1h = Enable UDMA_A clock during sleep mode
7-1 NU2 R 0h
0 RUNCLKEN R/W 0h
UDMA_A_RUN_CLK_ENABLE
0h = Disable UDMA_A clock during run mode
1h = Enable UDMA_A clock during run mode
To Next Page