Texas Instruments CC3235 SimpleLink Series - DES_IRQENABLE Register

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SWRU543–January 2019
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Data Encryption Standard Accelerator (DES)
18.5.19 DES_IRQENABLE Register (Offset = 1040h) [reset = 0h]
DES_IRQENABLE is shown in Figure 18-26 and described in Table 18-26.
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This register contains an enable bit for each unique interrupt generated by the module. It matches the
layout of DES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1.
Figure 18-26. DES_IRQENABLE Register
31 30 29 28 27 26 25 24
RESERVED
RO-0h
23 22 21 20 19 18 17 16
RESERVED
RO-0h
15 14 13 12 11 10 9 8
RESERVED
RO-0h
7 6 5 4 3 2 1 0
RESERVED M_DATA_OUT M_DATA_IN M_CONTEX_IN
RO-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-26. DES_IRQENABLE Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED RO 0h
2 M_DATA_OUT R/W 0h
If this bit is set to 1, the data output interrupt is enabled.
1 M_DATA_IN R/W 0h
If this bit is set to 1, the data input interrupt is enabled.
0 M_CONTEX_IN R/W 0h
If this bit is set to 1, the context interrupt is enabled.