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I2C Registers
233
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.6 I2CMRIS Register (Offset = 14h) [reset = 0h]
I2CMRIS is shown in Figure 7-19 and described in Table 7-10.
Return to Summary Table.
This register specifies whether an interrupt is pending.
Figure 7-19. I2CMRIS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFFRIS TXFERIS RXRIS TXRIS
R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
ARBLOSTRIS STOPRIS STARTRIS NACKRIS DMATXRIS DMARXRIS CLKRIS RIS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-10. I2CMRIS Register Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h
11 RXFFRIS R 0h
Receive FIFO Full Raw Interrupt Status
This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR
register.
0h = No interrupt
1h = The Receive FIFO Full interrupt is pending.
10 TXFERIS R 0h
Transmit FIFO Empty Raw Interrupt Status
This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR
register.
0h = No interrupt
1h = The Transmit FIFO Empty interrupt is pending.
Note that if the TXFERIS interrupt is cleared (by setting the TXFEIC
bit) when the TX FIFO is empty, the TXFERIS interrupt does not
reassert, even though the TX FIFO remains empty in this situation.
9 RXRIS R 0h
Receive FIFO Request Raw Interrupt Status
This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR
register.
0h = No interrupt
1h = The trigger level for the RX FIFO has been reached or there is
data in the FIFO and the burst count is zero. Thus, a RX FIFO
request interrupt is pending.
8 TXRIS R 0h
Transmit Request Raw Interrupt Status
This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR
register.
0h = No interrupt
1h = The trigger level for the TX FIFO has been reached and more
data is needed to complete the burst. Thus, a TX FIFO request
interrupt is pending.
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