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ADC_MODULE Registers
461
SWRU543–January 2019
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Analog-to-Digital Converter (ADC)
13.4.1.1 ADC_CTRL Register (offset = 0h) [reset = 0h]
ADC_CTRL is shown in Figure 13-3 and described in Table 13-3.
Figure 13-3. ADC_CTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ADC_EN_APP
S
R-0h R/W-0h
Table 13-3. ADC_CTRL Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 ADC_EN_APPS R/W 0h
ADC enable for application processor