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Texas Instruments CC3235 SimpleLink Series - INTCTRL Register; INTCTRL Register Field Descriptions

Texas Instruments CC3235 SimpleLink Series
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96
SWRU543January 2019
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Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Peripherals
3.3.1.12 INTCTRL Register (Offset = D04h) [reset = 0h]
INTCTRL is shown in Figure 3-12 and described in Table 3-15.
Return to Summary Table.
Figure 3-12. INTCTRL Register
31 30 29 28 27 26 25 24
NMISET RESERVED PENDSV UNPENDSV PENDSTSET PENDSTCLR RESERVED
R/W-0h R-0h R/W-0h W-0h R/W-0h W-0h R-0h
23 22 21 20 19 18 17 16
ISRPRE ISRPEND RESERVED VECPEND
R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
VECPEND RETBASE RESERVED
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
VECACT
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-15. INTCTRL Register Field Descriptions
Bit Field Type Reset Description
31 NMISET R/W 0h
NMI Set Pending
Because NMI is the highest-priority exception, normally the
processor enters the NMI exception handler as soon as it registers
the setting of this bit, and clears this bit on entering the interrupt
handler. A read of this bit by the NMI exception handler returns 1
only if the NMI signal is reasserted while the processor is executing
that handler.
0h (W) = On a write, no effect.
0h (R) = On a read, indicates an NMI exception is not pending.
1h (W) = On a write, changes the NMI exception state to pending.
1h (R) = On a read, indicates an NMI exception is pending.
30-29 RESERVED R 0h
28 PENDSV R/W 0h
PendSV Set Pending
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
0h (W) = On a write, no effect.
0h (R) = On a read, indicates a PendSV exception is not pending.
1h (W) = On a write, changes the PendSV exception state to
pending.
1h (R) = On a read, indicates a PendSV exception is pending.
27 UNPENDSV W 0h
PendSV Clear Pending
This bit is write onl on a register read, its value is unknown.
0h = On a write, no effect.
1h = On a write, removes the pending state from the PendSV
exception.
26 PENDSTSET R/W 0h
SysTick Set Pending
This bit is cleared by writing a 1 to the PENDSTCLR bit.
0h (W) = On a write, no effect.
0h (R) = On a read, indicates a SysTick exception is not pending.
1h (W) = On a write, changes the SysTick exception state to
pending.
1h (R) = On a read, indicates a SysTick exception is pending.

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