Texas Instruments CC3235 SimpleLink Series - Cortex -M4 Instruction Summary; Cortex Registers

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SWRU543–January 2019
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Cortex
®
-M4 Peripherals
3.3.1 Cortex Registers
Table 3-3 lists the memory-mapped Cortex registers. All register offset addresses not listed in Table 3-3
should be considered as reserved locations and the register contents should not be modified.
The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
NOTE: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-3. Cortex Registers
Offset Acronym Register Name Section
8h ACTLR Auxiliary Control Section 3.3.1.1
10h STCTRL SysTick Control and Status Register Section 3.3.1.2
14h STRELOAD SysTick Reload Value Register Section 3.3.1.3
18h STCURRENT SysTick Current Value Register Section 3.3.1.4
100h to 118h EN_0 to EN_6 Interrupt Set Enable Section 3.3.1.5
180h to 198h DIS_0 to DIS_6 Interrupt Clear Enable Section 3.3.1.6
200h to 218h PEND_0 to PEND_6 Interrupt Set Pending Section 3.3.1.7
280h to 298h UNPEND_0 to UNPEND_6 Interrupt Clear Pending Section 3.3.1.8
300h to 318h ACTIVE_0 to ACTIVE_6 Interrupt Active Bit Section 3.3.1.9
400h to 4C4h PRI_0 to PRI_49 Interrupt Priority Section 3.3.1.10
D00h CPUID CPU ID Base Section 3.3.1.11
D04h INTCTRL Interrupt Control and State Section 3.3.1.12
D08h VTABLE Vector Table Offset Section 3.3.1.13
D0Ch APINT Application Interrupt and Reset Control Section 3.3.1.14
D10h SYSCTRL System Control Section 3.3.1.15
D14h CFGCTRL Configuration Control Section 3.3.1.16
D18h SYSPRI1 System Handler Priority 1 Section 3.3.1.17
D1Ch SYSPRI2 System Handler Priority 2 Section 3.3.1.18
D20h SYSPRI3 System Handler Priority 3 Section 3.3.1.19
D24h SYSHNDCTRL System Handler Control and State Section 3.3.1.20
D28h FAULTSTAT Configurable Fault Status Section 3.3.1.21
D2Ch HFAULTSTAT Hard Fault Status Section 3.3.1.22
D38h FAULTDDR Bus Fault Address Section 3.3.1.23
F00h SWTRIG Software Trigger Interrupt Section 3.3.1.24