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Timer Registers
333
SWRU543–January 2019
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General-Purpose Timers
9.5.9 GPTMTAILR Register (offset = 28h) [reset = FFFFFFFFh]
GPTMTAILR is shown in Figure 9-13 and described in Table 9-17.
When a GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the
upper 16 bits correspond to the contents of the GPTM Timer B Interval Load (GPTMTBILR) register). In a
16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
Figure 9-13. GPTMTAILR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAILR
R/W-FFFFFFFFh
Table 9-17. GPTMTAILR Register Field Descriptions
Bit Field Type Reset Description
31-0 TAILR R/W FFFFFFFFh
GPTM Timer A Interval Load Register. Writing this field loads the
counter for Timer A. A read returns the current value of
GPTMTAILR.
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