Texas Instruments CC3235 SimpleLink Series - APSPICLKCFG Register; APSPICLKCFG Register Field Descriptions

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.9 APSPICLKCFG Register (offset = 2Ch) [reset = 0h]
APSPICLKCFG is shown in Figure 15-12 and described in Table 15-12.
Figure 15-12. APSPICLKCFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED BAUDSEL
R-0h R/W-0h
15 14 13 12 11 10 9 8
NU1 DIVOFFTIM
R-0h R/W-0h
7 6 5 4 3 2 1 0
NU2 DIVONTIM
R-0h R/W-0h
Table 15-12. APSPICLKCFG Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 BAUDSEL R/W 0h
MCSPI_A1_BAUD_CLK_SEL
0h = crystal clock is used as baud clock for MCSPI_A1
1h = PLL divclk is used as baud clock for MCSPI_A1.
15-11 NU1 R 0h
10-8 DIVOFFTIM R/W 0h
MCSPI_A1_PLLCLKDIV_OFF_TIME Configuration of OFF-TIME for
dividing PLL clock (240 MHz) in generation of MCSPI_A1 func-clk:
000h = 1
001h = 2
010h = 3
011h = 4
100h = 5
101h = 6
110h = 7
111h = 8
7-3 NU2 R 0h
2-0 DIVONTIM R/W 0h
MCSPI_A1_PLLCLKDIV_ON_TIME Configuration of ON-TIME for
dividing PLL clock (240 MHz) in generation of MCSPI_A1 func-clk:
000h = 1
001h = 2
010h = 3
011h = 4
100h = 5
101h = 6
110h = 7
111h = 8