Texas Instruments CC3235 SimpleLink Series - Fault Status and Fault Address Registers

Functional Description www.ti.com
70
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Processor
2.2.5.2 Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 in
Section 3.3.1.17). Software can disable execution of the handlers for these faults (see SYSHNDCTRL).
Usually the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another fault
handler as described in Section 2.2.4.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority
escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault
occurs because a fault handler cannot preempt itself, because it must have the same priority as the
current priority level.
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation
happens because the handler for the new fault cannot preempt the fault handler that is currently
executing.
• An exception handler causes a fault for which the priority is the same as or lower than the exception
that is currently executing.
• A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate
to a hard fault. Thus, if a corrupted stack causes a fault, the fault handler executes even though the stack
push for the handler failed. The fault handler operates but the stack contents are corrupted.
NOTE: Only reset and NMI can preempt the fixed-priority hard fault. A hard fault can preempt any
exception other than reset, NMI, or another hard fault.
2.2.5.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory-management faults, the
fault address register indicates the address accessed by the operation that caused the fault, as shown in
Table 2-9.
Table 2-9. Fault Status and Fault Address Registers
Handler Status Register Name Address Register Name Register Description
Hard fault Hard Fault Status
(HFAULTSTAT)
– Section 3.3.1.22
Memory-management fault Memory Management Fault
Status (MFAULTSTAT)
Memory Management Fault
Address (MMADDR)
Section 3.3.1.23
Bus fault Bus Fault Status
(BFAULTSTAT)
Bus Fault Address
(FAULTADDR)
Section 3.3.1.23
Usage fault Usage Fault Status
(UFAULTSTAT)
– Section 3.3.1.23
2.2.5.4 Lockup State
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers.
When the processor is in the lockup state, it does not execute any instructions. The processor remains in
lockup state until it is reset, an NMI occurs, or it is halted by a debugger.