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Functional Description
71
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Processor
2.2.6 Power Management
The CC32xx Wi-Fi microcontroller is a multiprocessor system-on-chip. An advanced power-management
scheme has been implemented at chip level that delivers the best-in-class energy efficiency across a wide
class of application profiles, while handling the asynchronous sleep-wake requirements of multiple high-
performance processors and Wi-Fi radio subsystems. The Cortex
®
-M4 application processor subsystem
(consisting of the CM4 core and application peripherals) is a subset of this.
In the chip-level power-management scheme, the application program is unaware of the power state
transitions of the other subsystems. This approach insulates the user from the complexities of a
multiprocessor system and simplifies the application development process.
From the standpoint of the Cortex
®
-M4 application processor, CC32xx supports the SLEEP mode similar
to those in discrete microcontrollers. In addition to SLEEP mode, additional modes are offered that
consume much less power:
• Low-Power Deep-Sleep (LPDS) mode:
– Recommended for ultra-low power always-connected cloud and Wi-Fi applications
– Up to 256KB of SRAM retention and fast wakeup (<5 mS)
– When networking and Wi-Fi subsystems are disabled, the MCU draws less than 100 µA with
256KB of SRAM retained (code and data). Total system current (including Wi-Fi and network
periodic wakeup) as low as 700 µA
– Processor and peripheral registers are not retained. Global always ON configurations at SoC level
are retained
• Hibernate (HIB) Mode:
– Recommended for ultra-low power infrequently connected cloud and Wi-Fi applications
– Ultra low current of 4 µA, including RTC
– Wake on RTC or selected GPIO
– No SRAM or logic retention. 2 × 32-bit register retention
• Shutdown Mode (choose this mode when periodic activity is required and the period between cycles is
long):
– Lowest power mode of about 1 µA
– System including RTC and memories are off
– Cold boot initialization is required
LPDS and HIB modes are discussed in more detail in the Power Clock and Reset Management chapter.
Figure 2-7 shows the architecture of the CC32xx SoC level power management, especially from the
application point of view.
The Cortex
®
-M4 processor implementation inside the CC32xx multiprocessor SoC has a few differences
when compared to a discrete MCU. While SLEEP mode is supported, in the CC32xx this mode is limited
in energy consumption savings.
Ultra-low power applications should be architected such that time spent in LPDS or hibernate mode is
maximized. The Cortex
®
-M4 application processor can be configured wake up on selected events, for
example network events such as an incoming data packet, timer, or I/O pad toggle. The time spent in
RUN (or ACTIVE) state should then be minimized. The dedicated Cortex
®
-M4 application processor in
CC32xx is particularly suited for this mode of operation due to its advanced power management, DMA,
zero wait-state multi-layer AHB interconnect, fast execution and retention over the entire range of zero
wait-state SRAM.
• SLEEP: Sleep mode stops the processor clock (clock gating).
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