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AES Functional Description
613
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Advance Encryption Standard Accelerator (AES)
Figure 17-1. AES Block Diagram
AES is an efficient implementation of the Rijndael cipher (the AES algorithm) and a 128-bit polynomial
multiplication (referred to here as GHASH, according to the AES-GCM specification). Rijndael is a block
cipher in which each data block is 128 bits. The polynomial multiplication multiplies two 128-bit vectors
using the smallest 128-bit irreducible polynomial, represented by the following 128-bit string: {0
120}||10000111. The two implementations are combined into the AES wide-bus engine.
Depending on the availability of context and data, the AES wide-bus engine is automatically triggered to
process the data. The AES wide-bus engine is directly connected to the context and data registers, so that
it can immediately start processing when all data is available. The AES wide-bus engine also interfaces to
the I/O control FSM/µDMA request interface.
AES comprises the following major functional blocks:
• Global control FSM and µDMA interface
• Register interface module
• The AES wide-bus engine
The AES wide-bus engine, which is the major top-level component, comprises the following functional
blocks:
• Mode control FSM: Manages the data flow to and from the AES wide-bus engine and starts each
encryption or decryption operation
• Feedback modes: The logic that implements the various feedback modes supported by AES.
• GHASH core: The polynomial multiplication algorithm used for AES-GCM
• AES key scheduler: Generates AES encryption and decryption (round) keys
• AES encryption core: The AES encryption algorithm
• AES decryption core: The AES decryption algorithm
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