AES Overview
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SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Advance Encryption Standard Accelerator (AES)
17.1 AES Overview
This section introduces the advanced encryption standard (AES), and describes the AES main functions
and connections in the device.
The AES security modules provide hardware-accelerated data encryption and decryption operations
based on a binary key. The AES is a symmetric cipher module that supports a 128-, 192-, or 256-bit key
in hardware for encryption and decryption. The AES module is based on a symmetric algorithm, meaning
that the encryption and decryption keys are identical. To encrypt data means to convert it from plaintext to
an unintelligible form called cipher text. Decrypting cipher text converts previously encrypted data to its
original plaintext form.
The main features of the AES accelerator follow:
• Support for basic AES encrypt and decrypt operations:
– Galois/Counter mode (GCM), with basic GHASH operation
– Counter mode with CBC-MAC (CCM)
– XTS mode
• Availability of the following feedback operating modes:
– Electronic code book mode (ECB)
– Cipher block chaining mode (CBC)
– Counter mode (CTR)
– Cipher feedback mode (CFB), 128-bit
– F8 mode
• Key sizes: 128, 192, and 256 bits
• Support for CBC_MAC and Fedora 9 (F9) authentication modes
• Basic GHASH operation (when selecting no encryption)
• Key scheduling in hardware
• Support for µDMA transfers
• Fully synchronous design
17.2 AES Functional Description
The following sections describe the features of the AES module.
17.2.1 AES Block Diagram
Figure 17-1 shows the AES block diagram. A single-core/dual-interface architecture is used.
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