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UART Registers
193
SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
6.3.8 UARTIFLS Register (Offset = 34h) [reset = 12h]
UARTIFLS is shown in Figure 6-10 and described in Table 6-10.
Return to Summary Table.
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the
FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the level.
That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if
the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the
9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the
half-way mark.
Figure 6-10. UARTIFLS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RXIFLSEL TXIFSEL
R-0h R/W-2h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-10. UARTIFLS Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5-3 RXIFLSEL R/W 2h
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
0h = Reserved
1h = RX FIFO full
2h = RX FIFO full (default)
3h = RX FIFO full
4h = RX FIFO full
2-0 TXIFSEL R/W 2h
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
0h = Reserved
1h = TX FIFO empty
2h = TX FIFO empty (default)
3h = TX FIFO empty
4h = TX FIFO empty
Note: If the EOT bit in UARTCTL is set, the transmit interrupt is
generated once the FIFO is completely empty and all data including
stop bits have left the transmit serializer. In this case, the setting of
TXIFLSEL is ignored.
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