UART Registers
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SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
Table 6-9. UARTCTL Register Field Descriptions (continued)
Bit Field Type Reset Description
11 RTS R/W 0h
Request to Send
When RTSEN is clear, the status of this bit is reflected on the
U1RTS signal. If RTSEN is set, this bit is ignored on a write and
should be ignored on read.
10 DTR R/W 0h
Reserved
9 RXE R/W 1h
UART Receive Enable
0h = The receive section of the UART is disabled.
1h = The receive section of the UART is enabled. If the UART is
disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
8 TXE R/W 1h
UART Transmit Enable
If the UART is disabled in the middle of a transmission, it completes
the current character before stopping.
0h = The transmit section of the UART is disabled.
1h = The transmit section of the UART is enabled.
Note: To enable transmission, the UARTEN bit must also be set.
7 LBE R/W 0h
UART Loop Back Enable
0h = Normal operation.
1h = The UnTx path is fed through the UnRx path.
6 RESERVED R 0h
5 HSE R/W 0h
High-Speed Enable
0h = The UART is clocked using the system clock divided by 16.
1h = The UART is clocked using the system clock divided by 8.
Note: System clock used is also dependent on the baud-rate divisor
configuration. The state of this bit has no effect on clock generation
in ISO 7816 smart card mode (the SMART bit is set).
4 EOT R/W 0h
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS
register.
0h = The TXRIS bit is set when the transmit FIFO condition specified
in UARTIFLS is met.
1h = The TXRIS bit is set only after all transmitted data, including
stop bits, have cleared the serializer.
3 RESERVED R 0h
2 RESERVED R 0h
1 SIREN R/W 0h
RESERVED
0 UARTEN R/W 0h
UART Enable
If the UART is disabled in the middle of transmission or reception, it
completes the current character before stopping.
0h = The UART is disabled.
1h = The UART is enabled.