DMA_IMS Register (offset = 90h) [reset = 0h]
www.ti.com
788
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
CC3235x Device Miscellaneous Registers
B.2 DMA_IMS Register (offset = 90h) [reset = 0h]
Register mask: FF0Fh
DMA_IMS is shown in Figure B-2 and described in Table B-3.
Figure B-2. DMA_IMS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD
R-X R/W-0h R/W-0h R/W-0h R/W-0h
Table B-3. DMA_IMS Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R X
15-12 ADCWR R/W 0h
ADC_WR_DMA_DONE_INT_MASK_SET
bit 15: ADC channel 6 DMA Done IRQ
bit 14: ADC channel 4 DMA Done IRQ
bit 13: ADC channel 2 DMA Done IRQ
bit 12: ADC channel 0 DMA Done IRQ
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
11 MCASPWR R/W 0h
MCASP_WR_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
10 MCASPRD R/W 0h
MCASP_RD_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
9 CAMEMPT R/W 0h
CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
8 CAMFULL R/W 0h
CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
7-4 RESERVED R X
3 APSPIWR R/W 0h
APPS_SPI_WR_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
2 APSPIRD R/W 0h
APPS_SPI_RD_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
1 SDIOMWR R/W 0h
SDIOM_WR_DMA_DONE_INT_MASK_SET
0h = No effect
1h = Set mask of the corresponding DMA DONE IRQ
To Next Page