Rpullup Rpullup
I2CSCL I2CSDA
Tiva™
Microcontroller
SCL SDA
3rd Party Device
with
Interface
SCL SDA
3rd Party Device
SCL
SDA
I C Bus
2
I C
2
with
Interface
I C
2
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•
•
•
•
•
•
•
Functional Description
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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
Table 7-1. I2C Signals (64QFN)
Pin Name Pin Number
Pin Mux /
Pin
Assignment
Pin Type Buffer Type Description
I2C1SCL
Pin 30
Pin Y
I/O OD I2C1 clock. This signal has an active pullup.
I2C1SDA
Pin 29
Pin Q
Pin R
I/O OD I2C1 data
7.2 Functional Description
The CC32xx has one instance of an I2C module comprised of both master and slave functions, identified
by a unique address. A master-initiated communication generates the clock signal, SCL. For proper
operation, the SDA and SCL pin must be configured as an open-drain signal. Both SDA and SCL signals
must be connected to a positive supply voltage using a pullup resistor. Figure 7-2 shows a typical I2C bus
configuration. The typical pullups needed for proper operation are approximately 2 kΩ.
See Chapter 7 for I2C timing diagrams.
Figure 7-2. I2C Bus Configuration
7.2.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on CC32xx
microcontrollers. SDA is the bidirectional serial data line and SCL is the bidirectional serial clock line. The
bus is considered idle when both lines are high.
Every transaction on the I2C bus is 9 bits long, consisting of 8 data bits and 1 acknowledge bit. The
number of bytes per transfer (defined as the time between a valid START and STOP condition, described
in Section 7.2.1.1) is unrestricted, but each data byte must be followed by an acknowledge bit, and data
must be transferred to MSB first. When a receiver cannot receive another complete byte, the receiver
holds the clock line SCL low and forces the transmitter into a wait state. The data transfer continues when
the receiver releases the clock SCL.
7.2.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A high-
to-low transition on the SDA line while the SCL is high is defined as a START condition, and a low-to-high
transition on the SDA line while SCL is high is defined as a STOP condition. The bus is considered busy
after a START condition and free after a STOP condition (see Figure 7-3).
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