Texas Instruments CC3235 SimpleLink Series - DMA_IMR Register; DMA_IMR Register Field Descriptions; Type Reset Description RX

DMA_IMR Register (offset = 8Ch) [reset = FF0Fh] www.ti.com
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SWRU543–January 2019
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CC3235x Device Miscellaneous Registers
B.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
Register mask: FF0Fh
DMA_IMR is shown in Figure B-1 and described in Table B-2.
Figure B-1. DMA_IMR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
ADCWR MCASPWR MCASPRD CAMEMPT CAMFULL
R/W-Fh R/W-1h R/W-1h R/W-1h R/W-1h
7 6 5 4 3 2 1 0
RESERVED APSPIWR APSPIRD SDIOMWR SDIOMRD
R-X R/W-1h R/W-1h R/W-1h R/W-1h
Table B-2. DMA_IMR Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R X
15-12 ADCWR R/W Fh
ADC_WR_DMA_DONE_INT_MASK
bit 15: ADC channel 6 interrupt enable/disable
bit 14: ADC channel 4 interrupt enable/disable
bit 13: ADC channel 2 interrupt enable/disable
bit 12: ADC channel 0 interrupt enable/disable
0h = interrupt enabled
1h = disable corresponding interrupt
11 MCASPWR R/W 1h
MCASP_WR_DMA_DONE_INT_MASK
0h = interrupt enabled
1h = disable corresponding interrupt
10 MCASPRD R/W 1h
MCASP_RD_DMA_DONE_INT_MASK
0h = interrupt enabled
1h = disable corresponding interrupt
9 CAMEMPT R/W 1h
CAM_FIFO_EMPTY_DMA_DONE_INT_MASK
0h = interrupt enabled
1h = disable corresponding interrupt
8 CAMFULL R/W 1h
CAM_THRESHHOLD_DMA_DONE_INT_MASK
0h = interrupt enabled
1h = disable corresponding interrupt
7-4 RESERVED R X
3 APSPIWR R/W 1h
APPS_SPI_WR_DMA_DONE_INT_MASK
0h = interrupt enabled
1h = disable corresponding interrupt
2 APSPIRD R/W 1h
APPS_SPI_RD_DMA_DONE_INT_MASK
0h = interrupt enabled
1h = disable corresponding interrupt
1 SDIOMWR R/W 1h
SDIOM_WR_DMA_DONE_INT_MASK
0h = interrupt enabled
1h = disable corresponding interrupt