www.ti.com
Timer Registers
325
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
General-Purpose Timers
9.5.5 GPTMIMR Register (offset = 18h) [reset = 0h]
Register mask: 0h
GPTMIMR is shown in Figure 9-9 and described in Table 9-13.
This register allows software to enable or disable GPTM controller-level interrupts. Setting a bit enables
the corresponding interrupt, while clearing a bit disables it.
Figure 9-9. GPTMIMR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED DMABIM RESERVED TBMIM CBEIM CBMIM TBTOIM
R-X R/W-X R-X R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
RESERVED DMAAIM TAMIM RESERVED CAEIM CAMIM TATOIM
R-X R/W-X R/W-X R-X R/W-X R/W-X R/W-X
Table 9-13. GPTMIMR Register Field Descriptions
Bit Field Type Reset Description
31-14 RESERVED R X
13 DMABIM R/W X
GPTM Timer B DMA Done Interrupt Mask. The DMABIM values are
defined as follows:
0h = Interrupt is disabled.
1h = Interrupt is enabled.
12 RESERVED R X
11 TBMIM R/W X
GPTM Timer B Match Interrupt Mask. The TBMIM values are
defined as follows:
0h = Interrupt is disabled.
1h = Interrupt is enabled.
10 CBEIM R/W X
GPTM Timer B Capture Mode Event Interrupt Mask. The CBEIM
values are defined as follows:
0h = Interrupt is disabled.
1h = Interrupt is enabled.
9 CBMIM R/W X
GPTM Timer B Capture Mode Match Interrupt Mask. The CBMIM
values are defined as follows:
0h = Interrupt is disabled.
1h = Interrupt is enabled.
8 TBTOIM R/W X
GPTM Timer B Time-Out Interrupt Mask. The TBTOIM values are
defined as follows:
0h = Interrupt is disabled.
1h = Interrupt is enabled.
7-6 RESERVED R X
5 DMAAIM R/W X
GPTM Timer A DMA Done Interrupt Mask. The DMAAIM values are
defined as follows:
0h = Interrupt is disabled.
1h = Interrupt is enabled.
To Next Page