ADC_MODULE Registers
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SWRU543–January 2019
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Analog-to-Digital Converter (ADC)
13.4.1.17 ADC_CH0_FIFO_LVL Register (offset = 94h) [reset = 0h]
ADC_CH0_FIFO_LVL is shown in Figure 13-19 and described in Table 13-19.
Figure 13-19. ADC_CH0_FIFO_LVL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ADC_CHANNEL0_FIFO_LVL
R-0h R-0h
Table 13-19. ADC_CH0_FIFO_LVL Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h
2-0 ADC_CHANNEL0_FIFO_
LVL
R 0h
This register shows the current FIFO level. FIFO is 4 words wide.
Possible supported levels are 0x0 to 0x4.
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