Texas Instruments CC3235 SimpleLink Series - SHAMD5_IDIGEST_B Register; SHAMD5_IDIGEST_B Register Field Descriptions

www.ti.com SHA-MD5 Registers
717
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
SHA/MD5 Accelerator
19.2.10 SHAMD5_IDIGEST_B Register (Offset = 24h) [reset = 0h]
SHAMD5_IDIGEST_B is shown in Figure 19-14 and described in Table 19-21.
Return to Summary Table.
WRITE: Inner / Initial Digest [95:64] for MD5 [127:96] for SHA-1, [223:192] for SHA-2 / HMAC Key
[319:288] for HMAC key proc
READ: Intermediate / Inner Digest [95:64] for MD5 [127:96] for SHA-1, [223:192] for SHA-2 /
Result Digest/MAC [95:64] for MD5 [127:96] for SHA-1, [191:160] for SHA-2 224, [223:192] for SHA-2 256
Figure 19-14. SHAMD5_IDIGEST_B Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-21. SHAMD5_IDIGEST_B Register Field Descriptions
Bit Field Type Reset Description
31-0 DATA R/W 0h
Data