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SWRU543–January 2019
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Cortex
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-M4 Peripherals
3.3.1.23 FAULTDDR Register (Offset = D38h) [reset = 0h]
FAULTDDR is shown in Figure 3-23 and described in Table 3-26.
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The FAULTADDR register contains the address of the location that generated a bus fault. When an
unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction,
even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT) register indicate the
cause of the fault and whether the value in the FAULTADDR register is valid.
NOTE: This register can only be accessed from privileged mode.
Figure 3-23. FAULTDDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-26. FAULTDDR Register Field Descriptions
Bit Field Type Reset Description
31-0 ADDR R/W 0h
Fault Address
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds
the address of the location that generated the bus fault.
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