Texas Instruments CC3235 SimpleLink Series - XSTAT Register; XSTAT Register Field Descriptions

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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.24 XSTAT Register (Offset = C0h) [reset = 0h]
XSTAT is shown in Figure 12-27 and described in Table 12-29.
Return to Summary Table.
The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot
number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the
flag to clear it, the McASP logic has priority and the flag remains set. This also causes a new interrupt
request to be generated.
Figure 12-27. XSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED XERR
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED XSTAFRM XDATA XLAST XTDMSLOT RESERVED XSYNCERR XUNDRN
R-0h R/W-0h R/W-0h R/W-0h R-0h R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-29. XSTAT Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
8 XERR R/W 0h
XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR |
XCKFAIL | XDMAERR Allows a single bit to be checked to
determine if a transmitter error interrupt has occurred.
0h = No errors have occurred.
1h = An error has occurred.
7 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
6 XSTAFRM R/W 0h
Transmit start of frame flag. Causes a transmit interrupt (XINT), if
this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by
writing a 1 to this bit. Writing a 0 has no effect.
0h = No new transmit frame sync (AFSX) is detected.
1h = A new transmit frame sync (AFSX) is detected.
5 XDATA R/W 0h
Transmit data ready flag. Causes a transmit interrupt (XINT), if this
bit is set and XDATA in XINTCTL is set. This bit is cleared by writing
a 1 to this bit. Writing a 0 has no effect.
0h = XBUF is written and is full.
1h = Data is copied from XBUF to XRSR. XBUF is empty and ready
to be written. XDATA is also set when the transmit serializers are
taken out of reset. When XDATA is set, it always causes a DMA
event (AXEVT).
4 XLAST R/W 0h
Transmit last slot flag. XLAST is set along with XDATA, if the current
slot is the last slot in a frame. Causes a transmit interrupt (XINT), if
this bit is set and XLAST in XINTCTL is set. This bit is cleared by
writing a 1 to this bit. Writing a 0 has no effect.
0h = Current slot is not the last slot in a frame.
1h = Current slot is the last slot in a frame. XDATA is also set.