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I2S Registers
445
SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.21 AHCLKXCTL Register (Offset = B4h) [reset = 8000h]
AHCLKXCTL is shown in Figure 12-24 and described in Table 12-26.
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The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency
master clock (AHCLKX) and the transmit clock generator.
Figure 12-24. AHCLKXCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
HCLKXM RESERVED HCLKXDIV
R/W-1h R-0h R/W-0h
7 6 5 4 3 2 1 0
HCLKXDIV
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-26. AHCLKXCTL Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
15 HCLKXM R/W 1h
Transmit high-frequency clock source bit.
0h = Reserved
1h = Internal transmit high-frequency clock source from output of
programmable high clock divider.
14-12 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
11-0 HCLKXDIV R/W 0h
Transmit high-frequency clock divide ratio bits determine the divide-
down ratio from AUXCLK to AHCLKX.
0h = Divide-by-1
1h = Divide-by-2
2h - FFFh = Divide-by-3 to divide-by-4096
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