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Functional Description
127
SWRU543–January 2019
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Direct Memory Access (DMA)
4.2.8 Interrupts and Errors
When a µDMA transfer is complete, a dma_done signal is sent to the peripheral that initiated the µDMA
event. Interrupts can be enabled within the peripheral to trigger on µDMA transfer completion. If the
transfer uses the software µDMA channel, then the completion interrupt occurs on the dedicated software
µDMA interrupt vector. If the µDMA controller encounters a bus or memory protection error as it tries to
perform a data transfer, it disables the µDMA channel that caused the error and generates an interrupt on
the µDMA error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR)
register to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be
cleared by writing 1 to the ERRCLR bit.
4.3 Register Description
4.3.1 DMA Register Map
Table 4-5 lists the µDMA channel control structures and registers. The channel control structure shows the
layout of one entry in the channel control table. The channel control table is in system memory, and the
location is determined by the application; thus, the base address is N/A (not applicable) and noted as such
above the register descriptions. In Table 4-5, the offset for the channel control structure is the offset from
the entry in the channel control table. See Table 4-2 for a description of how the entries in the channel
control table are in memory. The µDMA register addresses are given as a hexadecimal increment, relative
to the µDMA base address of 0x400F.F000.
NOTE: The µDMA module clock must be enabled before the registers can be programmed. There
must be a delay of three system clocks after the µDMA module clock is enabled before any
µDMA module registers are accessed.
Table 4-5. µDMA Register Map
Offset Name Type Reset Description
µDMA Channel Control Structure (Offset from Channel Control Table Base)
0x000 DMA_SRCENDP R/W - DMA Channel Source Address End
Pointer
0x004 DMA_DSTENDP R/W - DMA Channel Destination Address End
Pointer
0x008 DMA_CHCTL R/W - DMA Channel Control Word
µDMA Registers (Offset from µDMA Base Address)
0x000 DMA_STAT RO 0x001F.0000
0x004 DMA_CFG WO - DMA Configuration
0x008 DMA_CTLBASE R 0x0000.0000 DMA Channel Control Base Pointer
0x00C DMA_ALTBASE RO 0x0000.0200 DMA Alternate Channel Control Base
Pointer
0x010 DMA_WAITSTAT RO 0x03C3.CF00 DMA Channel Wait-on-Request Status
0x014 DMA_SWREQ WO - DMA Channel Software Request
0x018 DMA_USEBURSTSET R/W 0x0000.0000 DMA Channel Useburst Set
0x01C DMA_USEBURSTCLR WO - DMA Channel Useburst Clear
0x020 DMA_REQMASKSET R/W 0x0000.0000 DMA Channel Request Mask Set
0x024 DMA_REQMASKCLR WO - DMA Channel Request Mask Clear
0x028 DMA_ENASET R/W 0x0000.0000 DMA Channel Enable Set
0x02C DMA_ENACLR WO - DMA Channel Enable Clear
0x030 DMA_ALTSET R/W 0x0000.0000 DMA Channel Primary Alternate Set
0x034 DMA_ALTCLR WO - DMA Channel Primary Alternate Clear
0x038 DMA_PRIOSET R/W 0x0000.0000 DMA Channel Priority Set
0x03C DMA_PRIOCLR WO - DMA Channel Priority Clear
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