AES Registers
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SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.31 AES_TAG_OUT_2 Register (Offset = 78h) [reset = 0h]
AES_TAG_OUT_2 is shown in Figure 17-44 and described in Table 17-34.
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Figure 17-44. AES_TAG_OUT_2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HASH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-34. AES_TAG_OUT_2 Register Field Descriptions
Bit Field Type Reset Description
31-0 HASH R/W 0h
Hash result (MSW)
17.4.32 AES_TAG_OUT_3 Register (Offset = 7Ch) [reset = 0h]
AES_TAG_OUT_3 is shown in Figure 17-45 and described in Table 17-35.
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Figure 17-45. AES_TAG_OUT_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HASH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-35. AES_TAG_OUT_3 Register Field Descriptions
Bit Field Type Reset Description
31-0 HASH R/W 0h
Hash result (LSW)