Texas Instruments CC3235 SimpleLink Series - SPI_IRQSTATUS Register

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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6.3 SPI_IRQSTATUS Register (offset = 118h) [reset = 0h]
SPI_IRQSTATUS is shown in Figure 8-22 and described in Table 8-9.
The interrupt status regroups all the status of the module internal events that can generate an interrupt.
Figure 8-22. SPI_IRQSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED EOW WKS
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX_OVERFLO
W
RX_FULL TX_UNDERFL
OW
TX_EMPTY
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-9. SPI_IRQSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
17 EOW R/W 0h
End of word count event when a channel is enabled using the FIFO
buffer and the channel had sent the number of SPI word defined by
SPI_XFERLEVEL[WCNT].
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is pending
16 WKS R/W 0h
Wake Up event in slave mode when an active control signal is
detected on the SPIEN line programmed in the field
SPI_CHCONF[SPIENSLV].
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is pending
15-4 RESERVED R 0h
3 RX_OVERFLOW R/W 0h
Receiver register overflow (slave mode only).
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is pending
2 RX_FULL R/W 0h Receiver register full or almost full.
This bit indicate FIFO almost full status when built-in FIFO is use for
receive register (SPI_CHCONF[FFER] is set).
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is pending