Texas Instruments CC3235 SimpleLink Series - WDTRIS Register; WDTRIS Register Field Descriptions

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SWRU543–January 2019
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Watchdog Timer
10.3.5 WDTRIS Register (offset = 10h) [reset = 0h]
WDTRIS is shown in Figure 10-6 and described in Table 10-6.
This register is the raw interrupt status register. Watchdog interrupt events can be monitored through this
register if the controller interrupt is masked.
Figure 10-6. WDTRIS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED WDTRIS
R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 10-6. WDTRIS Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 WDTRIS R 0h
Watchdog Raw Interrupt Status
0h = The watchdog has not timed out.
1h = A watchdog time-out event has occurred.