UART Registers
www.ti.com
188
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Universal Asynchronous Receivers/Transmitters (UARTs)
6.3.5 UARTFBRD Register (Offset = 28h) [reset = 0h]
UARTFBRD is shown in Figure 6-7 and described in Table 6-7 .
Return to Summary Table.
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on
reset. When changing the UARTFBRD register, the new value does not take effect until transmission or
reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a
write to the UARTLCRH register.
Figure 6-7. UARTFBRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DIVFRAC
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-7. UARTFBRD Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5-0 DIVFRAC R/W 0h
Fractional Baud-Rate Divisor
To Next Page