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SWRU543–January 2019
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Cortex
®
-M4 Peripherals
3.3.1.1 ACTLR Register (Offset = 8h) [reset = 0h]
ACTLR is shown in Figure 3-1 and described in Table 3-4.
Return to Summary Table.
The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default
memory map, and interruption of multi-cycle instructions. By default, this register is set to provide optimum
performance from the Cortex-M4 application processor in the CC32xx, and does not normally require
modification.
NOTE: This register can only be accessed from privileged mode.
Figure 3-1. ACTLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DISOOFP DISFPCA
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED DISFOLD DISWBUF DISMCYC
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-4. ACTLR Register Field Descriptions
Bit Field Type Reset Description
31-10 RESERVED R 0h
9 DISOOFP R/W 0h
Disable out-of-order floating point
N/A for the CC32xx.
8 DISFPCA R/W 0h
7-3 RESERVED R 0h
2 DISFOLD R/W 0h
Disable IT Folding
In some situations, the processor can start executing the first
instruction in an IT block while it is still executing the IT instruction.
This behavior is called IT folding, and improves performance,
However, IT folding can cause jitter in looping. If a task must avoid
jitter, set the DISFOLD bit before executing the task, to disable IT
folding.
0h = No effect.
1h = Disables IT folding.
1 DISWBUF R/W 0h
Disable IT Folding
In some situations, the processor can start executing the first
instruction in an IT block while it is still executing the IT instruction.
This behavior is called IT folding, and improves performance.
However, IT folding can cause jitter in looping. If a task must avoid
jitter, set the DISFOLD bit before executing the task, to disable IT
folding.
0h = No effect.
1h = Disables IT folding.
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