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SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Peripherals
Table 3-4. ACTLR Register Field Descriptions (continued)
Bit Field Type Reset Description
0 DISMCYC R/W 0h
Disable Interrupts of Multiple Cycle Instructions
In this situation, the interrupt latency of the processor is increased
because any LDM or STM must complete before the processor can
stack the current state and enter the interrupt handler.
0h = No effect.
1h = Disables interruption of load multiple and store multiple
instructions.
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