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I2C Registers
235
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.7 I2CMMIS Register (Offset = 18h) [reset = 0h]
I2CMMIS is shown in Figure 7-20 and described in Table 7-11.
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This register specifies whether an interrupt was signaled.
Figure 7-20. I2CMMIS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFFMIS TXFEMIS RXMIS TXMIS
R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
ARBLOSTMIS STOPMIS STARTMIS NACKMIS DMATXMIS DMARXMIS CLKMIS MIS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-11. I2CMMIS Register Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h
11 RXFFMIS R 0h
Receive FIFO Full Interrupt Mask
This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR
register.
0h = No interrupt.
1h = An unmasked Receive FIFO Full interrupt was signaled and is
pending.
10 TXFEMIS R 0h
Transmit FIFO Empty Interrupt Mask
This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR
register.
0h = No interrupt.
1h = An unmasked Transmit FIFO Empty interrupt was signaled and
is pending.
9 RXMIS R 0h
Receive FIFO Request Interrupt Mask
This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR
register.
0h = No interrupt.
1h = An unmasked Receive FIFO Request interrupt was signaled
and is pending.
8 TXMIS R 0h
Transmit Request Interrupt Mask
This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR
register.
0h = No interrupt.
1h = An unmasked Transmit FIFO Request interrupt was signaled
and is pending.
7 ARBLOSTMIS R 0h
Arbitration Lost Interrupt Mask
This bit is cleared by writing a 1 to the ARBLOSTIC bit in the
I2CMICR register.
0h = No interrupt.
1h = An unmasked Arbitration Lost interrupt was signaled and is
pending.
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