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ADC_MODULE Registers
473
SWRU543–January 2019
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Analog-to-Digital Converter (ADC)
13.4.1.15 CHANNEL4FIFODATA Register (offset = 84h) [reset = 0h]
CHANNEL4FIFODATA is shown in Figure 13-17 and described in Table 13-17.
Figure 13-17. CHANNEL4FIFODATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO_RD_DATA
R-0h
Table 13-17. CHANNEL4FIFODATA Register Field Descriptions
Bit Field Type Reset Description
31-0 FIFO_RD_DATA R 0h
Read to this register returns ADC data, along with timestamp
information in the following format:
[1:0] : Reserved
[13:2] : ADC sample bits
[30:14]: Timestamp per ADC sample
[31] : Reserved
13.4.1.16 CHANNEL6FIFODATA Register (offset = 8Ch) [reset = 0h]
CHANNEL6FIFODATA is shown in Figure 13-18 and described in Table 13-18.
Figure 13-18. CHANNEL6FIFODATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO_RD_DATA
R-0h
Table 13-18. CHANNEL6FIFODATA Register Field Descriptions
Bit Field Type Reset Description
31-0 FIFO_RD_DATA R 0h
Read to this register returns ADC data, along with time stamp
information in the following format:
[1:0] : Reserved
[13:2] : ADC sample bits
[30:14]: Timestamp per ADC sample
[31] : Reserved