Functional Description
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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.2.1.8 Arbitration
A master may only start a transfer if the bus is idle. Two or more masters can generate a START
condition within minimum hold time of the START condition. In these situations, an arbitration scheme
occurs on the SDA line, while SCL is high. During arbitration, the first of the competing master devices to
place 1 (high) on SDA, while another master transmits 0 (low), switches off its data output stage, and
retires until the bus is idle again.
Arbitration can occur over several bits. The first stage is a comparison of address bits, and if both masters
are trying to address the same device, arbitration continues to the comparison of data bits.
If arbitration is lost when the I
2
C master is initiating a BURST with the TX FIFO enabled, the application
should execute the following steps to correctly handle the arbitration loss:
1. Flush and disable the TX FIFO.
2. Clear and mask the TXFE interrupt by clearing the TXFEIM bit in the I2CMIMR register.
When the bus is IDLE, the TX FIFO can be filled and enabled, the TXFE bit can be unmasked, and a new
BURST transaction can be initiated.
7.2.2 Supported Speed Modes
The I2C bus in the CC32xx can run in standard mode (100 kbps) or fast mode (400 kbps). The selected
mode should match the speed of the other I
2
C devices on the bus.
7.2.2.1 Standard and Fast Modes
Standard and fast modes are selected using a value in the I2C Master Timer Period (I2CMTPR) register
that results in an SCL frequency of 100 kbps for standard mode and 400 kbps for fast mode.
The I2C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
• CLK_PRD is the system clock period.
• SCL_LP is the low phase of SCL (fixed at 6).
• SCL_HP is the high phase of SCL (fixed at 4).
• TIMER_PRD is the programmed value in the I2CMTPR register.
This value is determined by replacing the known variables in Equation 5 and solving for TIMER_PRD.
The I
2
C clock period is calculated as in Equation 5:
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD (5)
For example:
CLK_PRD = 12.5 ns
TIMER_PRD = 39
SCL_LP = 6
SCL_HP = 4
yields a SCL frequency of:
1/SCL_PERIOD = 100 kHz
Table 7-2 gives examples of the timer periods to generate standard and fast mode SCL frequencies based
on the fixed 80-MHz system clock frequency.
Table 7-2. Timer Periods
System Clock Timer Period Standard Mode Timer Period Fast Mode
80 MHz 0x27 100 kbps 0x09 400 kbps
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