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Functional Description
209
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Inter-Integrated Circuit (I
2
C) Interface
7.2.1.6 Clock Low Time-out (CLTO)
The I2C slave can extend the transaction by periodically pulling the clock low to create a slow bit transfer
rate. The I2C module has a 12-bit programmable counter that tracks how long the clock has been held
low. The upper 8 bits of the count value are software-programmable through the I2C Master Clock Low
Timeout Count (I2CMCLKOCNT) register. The lower 4 bits are not user-visible, and are 0x0. The CNTL
value programmed in the I2CMCLKOCNT register must be greater than 0x01. The application can
program the 8 most significant bits of the counter to reflect the acceptable cumulative low period in
transaction. The count is loaded at the START condition and counts down on each falling edge of the
internal bus clock of the master. The internal bus clock generated for this counter runs at the programmed
I
2
C speed, even if SCL is held low on the bus. Upon reaching terminal count, the master state machine
forces ABORT on the bus by issuing a STOP condition at the instance of SCL and SDA release.
For example, if an I2C module operates at 100-kHz speed, programming the I2CMCLKOCNT register to
0xDA translates the value 0xDA0, because the lower 4 bits are set to 0x0. This translates to a decimal
value of 3488 clocks, or a cumulative clock low period of 34.88 ms at 100 kHz.
The CLKRIS bit in the I2C Master Raw Interrupt Status (I2CMRIS) register is set when the clock time-out
period is reached, allowing the master to start corrective action to resolve the remote slave state. In
addition, the CLKTO bit in the I2C Master Control/Status (I2CMCS) register is set; this bit is cleared when
a STOP condition is sent, or during the I2C master reset. The status of the raw SDA and SCL signals are
readable by software through the SDA and SCL bits in the I2C Master Bus Monitor (I2CMBMON) register
to help determine the state of the remote slave.
In the event of a CLTO condition, application software must choose how it intends to try bus recovery.
Most applications may try to manually toggle the I2C pins to force the slave to let go of the clock signal (a
common solution is to try to force a STOP on the bus). If a CLTO is detected before the end of a burst
transfer, and the bus is successfully recovered by the master, the master hardware tries to finish the
pending burst operation. Depending on the state of the slave after bus recovery, the actual behavior on
the bus varies. If the slave resumes in a state where it can acknowledge the master (where it was before
the bus hang), it continues where it left off. However, if the slave resumes in a reset state (or if a forced
STOP by the master causes the slave to enter the IDLE state), it may ignore the attempt of the master to
complete the burst operation, and NACK the first data byte that the master sends or requests.
Because the behavior of slaves cannot always be predicted, the application software should always write
the STOP bit in the I2C Master Configuration (I2CMCR) register during the CLTO interrupt service routine
(ISR). This limits the amount of data the master tries to send or receive upon bus recovery to a single
byte, and after the single byte is on the wire, the master issues a STOP. An alternative solution is to have
the application software reset the I2C peripheral before trying to manually recover the bus. This solution
allows the I2C master hardware to return to a known good (and idle) state before trying to recover a stuck
bus, and prevents any unwanted data from appearing on the wire.
NOTE: The master CLTO counter counts for the entire time SCL is held low continuously. If SCL is
deasserted at any point, the master CLTO counter is reloaded with the value in the
I2CMCLKOCNT register, and begins counting down from this value.
7.2.1.7 Dual Address
The I
2
C interface supports dual-address capability for the slave. The additional programmable address is
provided, and can be matched if enabled. In legacy mode with dual address disabled, the I
2
C slave
provides an ACK on the bus if the address matches the OAR field in the I2CSOAR register. In dual-
address mode, the I
2
C slave provides an ACK on the bus if either the OAR field in the I2CSOAR register
or the OAR2 field in the I2CSOAR2 register is matched. The enable for dual address is programmable
through the OAR2EN bit in the I2CSOAR2 register, and there is no disable on the legacy address.
The OAR2SEL bit in the I2CSCSR register indicates if the ACKed address is the alternate address or not.
When this bit is clear, it indicates either legacy operation or no address match.
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