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SPI Registers
303
SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6.10 SPI_RX Register (offset = 13Ch) [reset = 0h]
SPI_RX is shown in Figure 8-29 and described in Table 8-16.
This register contains a single SPI word received through the serial link, depending on SPI word length.
See Chapter Access to data registers for the list of supported accesses; the little-endian host accesses
the SPI 8-bit word on 0x00, while the big-endian host accesses it on 0x03.
Figure 8-29. SPI_RX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-16. SPI_RX Register Field Descriptions
Bit Field Type Reset Description
31-0 RDATA R 0h
Channel data received
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