Texas Instruments CC3235 SimpleLink Series - Vector Table

Exception number
(N+16)
.
.
.
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I
RQ number
(N)
2
1
0
-1
-2
-5
-10
-11
-12
-13
-14
Offset
0x040
+ 0x(N*4)
.
.
.
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
0x002C
0x0018
0x0014
0x0010
0x000C
0x0008
0x0004
0x0000
Vector
IRQ N
.
.
.
IRQ2
IRQ1
IRQ0
Systick
PendSV
Reserve
d
Reserved for Debug
SVCall
Reserved
Usage
fault Bus
fault
Memory management
fault Hard fault
NMI
Reset
Initial SP value
Functional Description www.ti.com
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SWRU543–January 2019
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Cortex
®
-M4 Processor
Figure 2-5. Vector Table
2.2.4.5 Exception Priorities
As shown in Table 2-6, all exceptions have an associated priority, with a lower assigned priority value
indicating an actual higher priority and configurable priorities for all exceptions except reset, hard fault,
and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have
a priority of 0.
NOTE: Configurable priority values for the CC32xx implementation are in the range from 0 to 7. This
means that the reset, hard fault, and NMI exceptions (NMI is reserved for use by the system)
with fixed negative priority values always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that
IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before
IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].