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I2C Registers
257
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.22 I2CSACKCTL Register (Offset = 820h) [reset = 0h]
I2CSACKCTL is shown in Figure 7-35 and described in Table 7-26.
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This register enables the I2C slave to NACK for invalid data or command or ACK for valid data or
command. The I2C clock is pulled low after the last data bit until this register is written.
Figure 7-35. I2CSACKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ACKOVAL ACKOEN
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-26. I2CSACKCTL Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 ACKOVAL R/W 0h
I2C Slave ACK Override Value
0h = An ACK is sent indicating valid data or command.
1h = A NACK is sent indicating invalid data or command.
0 ACKOEN R/W 0h
I2C Slave ACK Override Enable
0h = A response in not provided.
1h = An ACK or NACK is sent according to the value written to the
ACKOVAL bit.
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