Texas Instruments CC3235 SimpleLink Series - SLPTMRCFG Register; SLPTMRCFG Register Field Descriptions

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.47 SLPTMRCFG Register (offset = 114h) [reset = 0h]
SLPTMRCFG is shown in Figure 15-50 and described in Table 15-50.
Figure 15-50. SLPTMRCFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRCFG
R/W-0h
Table 15-50. SLPTMRCFG Register Field Descriptions
Bit Field Type Reset Description
31-0 TMRCFG R/W 0h
SLP_WAKE_TIMER_CFG Configuration (number of sysclks-80MHz)
for the Sleep wake-up timer.