SPI Registers
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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
Table 8-9. SPI_IRQSTATUS Register Field Descriptions (continued)
Bit Field Type Reset Description
1 TX_UNDERFLOW R/W 0h
Transmitter register underflow.
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is pending
0 TX_EMPTY R/W 0h Transmitter register empty or almost empty.
This bit indicate FIFO almost full status when built-in FIFO is use for
transmit register (SPI_CHCONF[FFEW] is set).
0h (W) = Event status bit unchanged
0h (R) = Event false
1h (W) = Event status bit is reset
1h (R) = Event is pending
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