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Register Description
129
SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.3.1 DMA_SRCENDP Register (offset = 0h) [reset = 0h]
DMA_SRCENDP is shown in Figure 4-4 and described in Table 4-7.
Figure 4-4. DMA_SRCENDP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-7. DMA_SRCENDP Register Field Descriptions
Bit Field Type Reset Description
31-0 ADDR R/W 0h Source Address End Pointer. This field points to the last address of
the DMA transfer source (inclusive).
If the source address is not incrementing (the SRCINC field in the
DMACHCTL register is 0x3), then this field points at the source
location itself (such as a peripheral data register).
4.3.3.2 DMA_DSTENDP Register (offset = 4h) [reset = 0h]
DMA_DSTENDP is shown in Figure 4-5 and described in Table 4-8.
Figure 4-5. DMA_DSTENDP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-8. DMA_DSTENDP Register Field Descriptions
Bit Field Type Reset Description
31-0 ADDR R/W 0h Destination Address End Pointer. This field points to the last address
of the DMA transfer destination (inclusive).
If the destination address is not incrementing (the DSTINC field in
the DMACHCTL register is 0x3), then this field points at the source
location itself (such as a peripheral data register).
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