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Timer Registers
317
SWRU543–January 2019
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General-Purpose Timers
9.5 Timer Registers
Table 9-8 lists the memory-mapped Timer registers. All register offset addresses not listed in Table 9-8
should be considered as reserved locations, and the register contents should not be modified.
Table 9-8. Timer Registers
Offset Acronym Register Name Section
0h GPTMCFG GPTM Configuration Section 9.5.1
4h GPTMTAMR GPTM Timer A Mode Section 9.5.2
8h GPTMTBMR GPTM Timer B Mode Section 9.5.3
Ch GPTMCTL GPTM Control Section 9.5.4
18h GPTMIMR GPTM Interrupt Mask Section 9.5.5
1Ch GPTMRIS GPTM Raw Interrupt Status Section 9.5.6
20h GPTMMIS GPTM Masked Interrupt Status Section 9.5.7
24h GPTMICR GPTM Interrupt Clear Section 9.5.8
28h GPTMTAILR GPTM Timer A Interval Load Section 9.5.9
2Ch GPTMTBILR GPTM Timer B Interval Load Section 9.5.10
30h GPTMTAMATCHR GPTM Timer A Match Section 9.5.11
34h GPTMTBMATCHR GPTM Timer B Match Section 9.5.12
38h GPTMTAPR GPTM Timer A Prescale Section 9.5.13
3Ch GPTMTBPR GPTM Timer B Prescale Section 9.5.14
40h GPTMTAPMR GPTM Timer A Prescale Match Section 9.5.15
44h GPTMTBPMR GPTM Timer B Prescale Match Section 9.5.16
48h GPTMTAR GPTM Timer A Section 9.5.17
4Ch GPTMTBR GPTM Timer B Section 9.5.18
50h GPTMTAV GPTM Timer A Value Section 9.5.19
54h GPTMTBV GPTM Timer B Value Section 9.5.20
6Ch GPTMDMAEV GPTM DMA Event Section 9.5.21
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