Texas Instruments CC3235 SimpleLink Series - XINTCTL Register; XINTCTL Register Field Descriptions

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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.23 XINTCTL Register (Offset = BCh) [reset = 0h]
XINTCTL is shown in Figure 12-26 and described in Table 12-28.
Return to Summary Table.
The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt
(XINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP conditions generates
XINT.
Figure 12-26. XINTCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
XSTAFRM RESERVED XDATA XLAST RESERVED XSYNCERR XUNDRN
R/W-0h R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-28. XINTCTL Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
7 XSTAFRM R/W 0h
Transmit start of frame interrupt enable bit.
0h = Interrupt is disabled. A transmit start of frame interrupt does not
generate a McASP transmit interrupt (XINT).
1h = Interrupt is enabled. A transmit start of frame interrupt
generates a McASP transmit interrupt (XINT).
6 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
5 XDATA R/W 0h
Transmit data ready interrupt enable bit.
0h = Interrupt is disabled. A transmit data ready interrupt does not
generate a McASP transmit interrupt (XINT).
1h = Interrupt is enabled. A transmit data ready interrupt generates a
McASP transmit interrupt (XINT).
4 XLAST R/W 0h
Transmit last slot interrupt enable bit.
0h = Interrupt is disabled. A transmit last slot interrupt does not
generate a McASP transmit interrupt (XINT).
1h = Interrupt is enabled. A transmit last slot interrupt generates a
McASP transmit interrupt (XINT).
3-2 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
1 XSYNCERR R/W 0h
Unexpected transmit frame sync interrupt enable bit.
0h = Interrupt is disabled. An unexpected transmit frame sync
interrupt does not generate a McASP transmit interrupt (XINT).
1h = Interrupt is enabled. An unexpected transmit frame sync
interrupt generates a McASP transmit interrupt (XINT).