DES Registers
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SWRU543–January 2019
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Data Encryption Standard Accelerator (DES)
18.5.17 DES_SYSCONFIG Register (Offset = 1034h) [reset = 0h]
DES_SYSCONFIG is shown in Figure 18-24 and described in Table 18-24.
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Figure 18-24. DES_SYSCONFIG Register
31 30 29 28 27 26 25 24
RESERVED
RO-0h
23 22 21 20 19 18 17 16
RESERVED
RO-0h
15 14 13 12 11 10 9 8
RESERVED
RO-0h
7 6 5 4 3 2 1 0
DMA_REQ_CO
NTEXT_IN_EN
DMA_REQ_DA
TA_OUT_EN
DMA_REQ_DA
TA_IN_EN
RESERVED
R/W-0h R/W-0h R/W-0h RO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-24. DES_SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED RO 0h
7 DMA_REQ_CONTEXT_IN
_EN
R/W 0h
If set to 1, the DMA context request is enabled.
0h = DMA disabled
1h = DMA enabled
6 DMA_REQ_DATA_OUT_
EN
R/W 0h
If set to 1, the DMA output request is enabled.
0h = DMA disabled
1h = DMA enabled
5 DMA_REQ_DATA_IN_EN R/W 0h
If set to 1, the DMA input request is enabled.
0h = DMA disabled
1h = DMA enabled
4-0 RESERVED RO 0h