Texas Instruments CC3235 SimpleLink Series - AES_IRQENABLE Register

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SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.36 AES_IRQENABLE Register (Offset = 90h) [reset = X]
AES_IRQENABLE is shown in Figure 17-49 and described in Table 17-39.
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This register contains an enable bit for each unique interrupt generated by the module. It matches the
layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1. An
interrupt that is enabled is propagated to the SINTREQUEST_x output. All interrupts must be enabled
explicitly by writing this register.
Figure 17-49. AES_IRQENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED CONTEXT_OU
T
DATA_OUT DATA_IN CONTEXT_IN
R-X R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-39. AES_IRQENABLE Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R X
3 CONTEXT_OUT R/W 0h
This bit indicates authentication tag (and IV) interrupts are active,
and triggers the interrupt output.
2 DATA_OUT R/W 0h
This bit indicates data output interrupt is active, and triggers the
interrupt output
1 DATA_IN R/W 0h
This bit indicates data input interrupt is active, and triggers the
interrupt output
0 CONTEXT_IN R/W 0h
This bit indicates context interrupt is active, and triggers the interrupt
output.