SHA-MD5 Registers
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SWRU543–January 2019
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SHA/MD5 Accelerator
19.2.39 DTHE_SHA_IM Register (Offset = 810h) [reset = X]
DTHE_SHA_IM is shown in Figure 19-43 and described in Table 19-50.
Return to Summary Table.
SHA/MD5 interrupt mask set register that allows the control of which interrupt source should interrupt the
processor.
Figure 19-43. DTHE_SHA_IM Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED Din Cout Cin
R-X R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-50. DTHE_SHA_IM Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
2 Din R/W 1h
Data in: this interrupt is raised when DMA writes last word of input
data to internal FIFO of the engine.
1 Cout R/W 1h
Context out: this interrupt is raised when DMA completes the output
context movement from internal register.
0 Cin R/W 1h
Context in: this interrupt is raised when DMA completes a context
write to internal register
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