ADC_MODULE Registers
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SWRU543–January 2019
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Analog-to-Digital Converter (ADC)
13.4.1.4 ADC_CH4_IRQ_EN Register (offset = 34h) [reset = 0h]
ADC_CH4_IRQ_EN is shown in Figure 13-6 and described in Table 13-6.
Figure 13-6. ADC_CH4_IRQ_EN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ADC_CHANNEL4_IRQ_EN
R-0h R/W-0h
Table 13-6. ADC_CH4_IRQ_EN Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3-0 ADC_CHANNEL4_IRQ_E
N
R/W 0h
Interrupt enable register for ADC channel
Bit 3: when 1 -> enable FIFO overflow interrupt
Bit 2: when 1 -> enable FIFO underflow interrupt
Bit 1: when 1 -> enable FIFO empty interrupt
Bit 0: when 1 -> enable FIFO full interrupt