Texas Instruments CC3235 SimpleLink Series - MCASPCLKCFG1 Register

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.39 MCASPCLKCFG1 Register (offset = B4h) [reset = 0h]
MCASPCLKCFG1 is shown in Figure 15-42 and described in Table 15-42.
Figure 15-42. MCASPCLKCFG1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED DIVIDRSWRST
R-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED SPARE
R-0h R/W-0h
7 6 5 4 3 2 1 0
SPARE
R/W-0h
Table 15-42. MCASPCLKCFG1 Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 DIVIDRSWRST R/W 0h
MCASP_FRAC_DIV_SOFT_RESET
0h = Do not assert the reset for MCASP frac clk-div
1h = Assert the reset for MCASP Frac-clk div
15-10 RESERVED R 0h
9-0 SPARE R/W 0h
MCASP_FRAC_DIV_PERIOD. This bit field is not used in hardware.
Can be used as a spare RW register.