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I2C Registers
239
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.9 I2CMCR Register (Offset = 20h) [reset = 0h]
I2CMCR is shown in Figure 7-22 and described in Table 7-13.
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This register configures the mode (master or slave), and sets the interface for test mode loopback.
Figure 7-22. I2CMCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SFE MFE RESERVED LPBK
R-0h R/W-0h R/W-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-13. I2CMCR Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5 SFE R/W 0h
I2C Slave Function Enable
0h = Slave mode is disabled.
1h = Slave mode is enabled.
4 MFE R/W 0h
I2C Master Function Enable
0h = Master mode is disabled.
1h = Master mode is enabled.
3-1 RESERVED R 0h
0 LPBK R/W 0h
I2C Loopback
0h = Normal operation.
1h = The controller in a test mode loopback configuration.
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