I2C Registers
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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.19 I2CSMIS Register (Offset = 814h) [reset = 0h]
I2CSMIS is shown in Figure 7-32 and described in Table 7-23.
Return to Summary Table.
This register specifies whether an interrupt was signaled.
Figure 7-32. I2CSMIS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFFMIS
R-0h R-0h
7 6 5 4 3 2 1 0
TXFEMIS RXMIS TXMIS DMATXMIS DMARXMIS STOPMIS STARTMIS DATAMIS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-23. I2CSMIS Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
8 RXFFMIS R 0h
Receive FIFO Full Interrupt Mask
This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR
register.
0h = No interrupt.
1h = An unmasked Receive FIFO Full interrupt was signaled and is
pending.
7 TXFEMIS R 0h
Transmit FIFO Empty Interrupt Mask
This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR
register.
0h = No interrupt.
1h = An unmasked Transmit FIFO Empty interrupt was signaled and
is pending.
6 RXMIS R 0h
Receive FIFO Request Interrupt Mask
This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR
register.
0h = No interrupt.
1h = An unmasked Receive FIFO Request interrupt was signaled
and is pending.
5 TXMIS R 0h
Transmit FIFO Request Interrupt Mask
This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR
register.
0h = No interrupt.
1h = An unmasked Transmit FIFO Request interrupt was signaled
and is pending.
4 DMATXMIS R 0h
Transmit DMA Masked Interrupt Status
This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked transmit DMA complete interrupt was signaled is
pending.
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