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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.17 DMA_ERRCLR Register (offset = 4Ch) [reset = 0h]
DMA_ERRCLR is shown in Figure 4-23 and described in Table 4-27.
This register is used to read and clear the DMA bus error status. The error status is set if the DMA
controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that
channel is automatically disabled by the DMA controller. The other channels are unaffected.
Figure 4-23. DMA_ERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ERRCLR
R-0h R/W1C-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-27. DMA_ERRCLR Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 ERRCLR R/W1C 0h
DMA Bus Error Status
0h = No bus error is pending.
1h = A bus error is pending.
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